• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention discloses a method for manufacturing a fringe field switching mode liquid crystal display device. Here, a counter electrode, gate bus line and common electrode line are formed by one photolithography process including: a first process for coating a resist film on the MoW film; a second process for forming a resist pattern consisting of first and second patterns respectively covering gate bus line and common electrode line formation regions and maintaining a coating thickness, and a third pattern covering a counter electrode formation region and partially maintaining the coating thickness, by exposing/developing the resist film; a third process for forming the gate bus line and the common electrode line by dry-etching the MoW film using the resist pattern as an etch barrier, the first and second patterns being partially removed, the third pattern being completely removed, the MoW film on the counter electrode formation region being partially removed; a fourth process for forming the counter electrode by wet-etching the ITO film using the remained resist pattern and MoW film as an etch barrier; and a fifth process for removing the remained resist pattern and MoW film.
    公开号:US20010007779A1
    申请号:US09/737,670
    申请日:2000-12-15
    公开日:2001-07-12
    发明作者:Kyung Ha Lee；Sung Hyun Cho
    申请人:Hynix Semiconductor Inc；
    IPC主号:H01L27-124
    专利说明:
    [0001] 1. Field of the Invention [0001]
    [0002] The present invention relates to a method for manufacturing a liquid crystal display device, and in particular to a method for manufacturing a fringe field switching mode liquid crystal display device which can reduce a manufacturing time and cost. [0002]
    [0003] 2. Description of the Background Art [0003]
    [0004] An in-plane switching (IPS) mode liquid crystal display device has been suggested to improve a narrow field angle of a TN mode liquid crystal display device. As publicly known, in the IPS mode liquid crystal display device, a counter electrode and a pixel electrode for driving a liquid crystal are aligned in parallel on an identical substrate. The field angle is improved according to a major axis of liquid crystal molecules, regardless of a direction in which a user watches a screen. The IPS mode liquid crystal display device has a wider field angle than the TN mode liquid crystal display device. However, the counter electrode and the pixel electrode consist of an opaque metal, and thus its aperture ratio and transmittance are poor. [0004]
    [0005] Accordingly, in order to improve the aperture ratio and transmittance of the IPS mode liquid crystal display device, there has been taught a fringe field switching mode liquid crystal display device(hereinafter, referred to as ‘FFS mode LCD’) wherein the liquid crystal molecules are driven by a fringe field. [0005]
    [0006] In the FFS mode LCD, the counter electrode and the pixel electrode consist of a transparent material such as an indium tin oxide (ITO), and an interval between the counter electrode and the pixel electrode is smaller than an interval between upper and lower substrates. In addition, the counter electrode and the pixel electrode have a sufficient width so that the liquid crystal molecules on the electrodes can be all driven. Since the electrodes consist of the transparent material, the FFS mode LCD obtains a more improved aperture ratio than the IPS mode LCD. Moreover, the light permeability occurs in the electrodes, and thus the FFS mode LCD obtains a more improved transmittance than the IPS mode LCD. [0006]
    [0007] FIG. 1 is a cross-sectional diagram illustrating the lower substrate in the conventional FFS mode LCD. A method manufacturing the FFS mode LCD will now be described with reference to FIG. 1. [0007]
    [0008] An ITO film is deposited on a glass substrate [0008] 1. The ITO film is patterned according to a first photolithography process, thereby forming a counter electrode 2 in a plate shape. An MoW film is deposited on the counter electrode 2 and the glass substrate 1 and then the MoW film is patterned according to a second photolithography process, thereby forming a gate bus line 3 and a common electrode line 4.
    [0009] A gate insulating film [0009] 5 is formed over the resultant structure. An undoped amorphous silicon film and a doped amorphous silicon film are sequentially deposited on the gate insulating film 5 and then the doped amorphous silicon film and the undoped amorphous silicon film are patterned according to a third lithography process, thereby forming an ohmic contact layer 7 and a channel layer 6. A metal film for source/drain is deposited over the resultant structure. The metal film is patterned according to a fourth lithography process, thereby forming a data bus line(not shown) including source and drain electrodes 8 a, 8 b. As a result, a thin film transistor (TFT) is formed.
    [0010] A passivation film [0010] 9 is deposited over the resultant structure. Thereafter, the passivation film 9 is etched according to a fifth photolithography process so that the source electrode 8 a can be partially exposed. An ITO film is deposited on the passivation film 9 and then patterned according to a sixth photolithography process, thereby forming a comb-shaped pixel electrode 10 having a few branches and contacting with the source electrodes 8 a of the TFT.
    [0011] However, the conventional method for manufacturing the FFS mode LCD has a disadvantage in that six photolithography processes are performed to form the lower substrate, which results in an increased manufacturing time and cost. [0011]
    [0012] In more detail, the photolithography process includes a process for forming a resist pattern such as resist coating, exposure and development processes, an etching process using the resist pattern, and a process for removing the resist pattern. Therefore, even one photolithography process takes a long time. Accordingly, the conventional method for manufacturing the FFS mode LCD by performing the six photolithography processes is not advantageous in productivity. In addition, the etching process requires a mask for exposure that is very expensive. Thus, the six photolithography processes require six masks for exposure. As a result, the conventional method for manufacturing the FFS mode LCD is not advantageous in cost, either. [0012] SUMMARY OF THE INVENTION
    [0013] Therefore, an object of the present invention is to provide a method for manufacturing a fringe field switching mode liquid crystal display device which can reduce a manufacturing time and cost. [0013]
    [0014] In order to achieve the above-described object of the present invention, a method for manufacturing a fringe field switching mode liquid crystal display device includes the steps of: forming a counter electrode, a gate bus line and a common electrode line at the same time, by sequentially depositing an indium tin oxide film and an MoW film on a glass substrate, and patterning the MoW film and the ITO film according to a first photolithography process; depositing a gate insulating film over the resultant structure; forming a stacked channel layer and ohmic contact layer on a predetermined portion of the gate insulating film, by using a second photolithography process; forming a data bus line including source/drain electrodes on the ohmic contact layer and the gate insulting film, by using a third photolithography process; forming a passivation film to expose the source electrode over the resultant structure, by using a fourth photolithography process; and forming a pixel electrode of a comb shape in contact with the source electrode on the passivation film, by using a fifth photolithography process, wherein the first photolithography process comprises: a first process for coating a resist film on the MoW film; a second process for forming a resist pattern consisting of first and second patterns respectively covering gate bus line and common electrode line formation regions and maintaining a coating thickness, and a third pattern covering a counter electrode formation region and partially maintaining the coating thickness, by exposing and developing the resist film; a third process for forming the gate bus line and the common electrode line by dry-etching the MoW film using the resist pattern as an etch barrier, the first and second patterns being partially removed, the third pattern being completely removed, the MoW film on the counter electrode formation region being partially removed; a fourth process for forming the counter electrode by wet-etching the ITO film using the remained resist pattern and MoW film as an etch barrier; and a fifth process for removing the remained resist pattern and MoW film. [0014] BRIEF DESCRIPTION OF THE DRAWINGS
    [0015] The present invention will become better understood with reference to the accompanying drawings that are given only by way of illustration and thus are not limitative of the present invention, wherein: [0015]
    [0016] FIG. 1 is a cross-sectional diagram illustrating a lower substrate in a conventional FFS mode LCD; [0016]
    [0017] FIGS. 2A to [0017] 2C are cross-sectional diagrams illustrating sequential steps of a method for manufacturing an FFS mode LCD in accordance with the present invention;
    [0018] FIGS. 3A to [0018] 3D are cross-sectional diagrams illustrating sequential steps of a first photolithography process in accordance with the present invention; and
    [0019] FIGS. 4A to [0019] 4C are cross-sectional diagrams illustrating sequential steps of a method for forming a resist pattern in accordance with the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
    [0020] FIGS. 2A to [0020] 2C are cross-sectional diagrams illustrating sequential steps of a method for manufacturing a fringe field switching mode liquid crystal display device (hereinafter, referred to as ‘FFS mode LCD’) in accordance with the present invention.
    [0021] Referring to FIG. 2A, a glass substrate [0021] 11 consists of a transparent insulating substrate. An indium tin oxide (ITO) film and a MoW film are sequentially deposited on the glass substrate 11. The ITO film is a transparent metal film for a counter electrode, and the MoW film is an opaque metal film for a gate bus line and a common electrode line. The MoW film and the ITO film are patterned according to a first photolithography process, thereby forming a counter electrode 12 a, a gate bus line 13 a and a common electrode line 14 a at the same time.
    [0022] Herein, the first photolithography process for forming the counter electrode [0022] 12 a, gate bus line 13 a and common electrode line 14 a will now be explained with reference to FIGS. 3A to 3D.
    [0023] In FIG. 3A, a resist pattern [0023] 32 is formed on the MoW film 13 as an etch barrier. The resist pattern 32 has a different thickness in each region. That is, the resist pattern 32 consists of a first pattern 32 a covering a gate bus line formation region, a second pattern 32 b covering a common electrode line formation region, and a third pattern 32 c covering a counter electrode formation region. The third pattern 32 c has a smaller thickness than the first and second patterns 32 a, 32 b.
    [0024] In order to form such a resist pattern [0024] 32, an exposure process is performed on the resist film by employing a semipermeable mask.
    [0025] As shown in FIGS. 4A and 4B, in the semipermeable mask [0025] 50, a chrome pattern 42 for defining a light permeable region and a shield region is formed on a quartz substrate 41, and semipermeable patterns 43 a, 43 b for decreasing a light permeable amount are formed in a predetermined permeable region. A stripe type chrome pattern 43 as shown in FIG. 4A and a low permeable metal film 43 b such as an ITO film as shown in FIG. 4B may be used as the semipermeable patterns 43 a, 43 b.
    [0026] In the exposure process using the semipermeable mask [0026] 50, the ITO film 12 is deposited at a thickness below 1,000 Å, preferably from 500 to 1,000 Å, and the resist film 30 is coated at a thickness over 2 μm, preferably from 2 to 3 μm. As a result of the exposure process, a part of the resist film 30 exposed through the light permeable region where the semipermeable patterns 43 a, 43 b have not been formed is completely exposed, but the other part of the resist film 30 exposed through the light permeable region where the semipermeable patterns 43 a, 43 b have been formed is half exposed. As shown in FIG. 4C, when the completely and half exposed resist film 30 is developed, the resist pattern 32 has a different thickness in each region.
    [0027] In FIG. 3B, the MoW film [0027] 13 is dry-etched by using the resist pattern 32 as an etch barrier, thereby forming a gate bus line 13 a and a common electrode line 14 a. Herein, the first and second patterns 32 a, 32 b of the resist pattern 32 partially remain on the gate bus line 13 a and the common electrode line 14 a, but the third pattern thereof does not remain on the counter electrode formation region. In addition, the MoW film 13 partially remains on the counter electrode formation region. The dry etching process is performed by employing a mixed gas of an excited gas such as SF6, CF4 or He and O2 gas. A flow rate ratio of the O2 gas and the excited gas is represented by the following equation 1. O 2     gas     flow     rate excited     gas     flow     rate < 1 equation 1
    [0028] In FIG. 3C, the ITO film is wet-etched by using the residual resist patterns [0028] 32 a, 32 b and MoW film 13 as an etch barrier, thereby forming a counter electrode 12 a.
    [0029] In FIG. 3D, the resist patterns [0029] 32 a, 32 b and the MoW film 13 are removed according to a dry strip process, and thus the first photolithography process for forming the counter electrode 12 a, the gate bus line 13 a and the common electrode line 14 a is finished.
    [0030] As described above, the counter electrode [0030] 12 a, the gate bus line 13 a and the common electrode line 14 a are formed according to one photolithography process. That is to say, the etching process is carried out two times on the counter electrode 12 a, the gate bus line 13 a and the common electrode line 14 a, but the resist coating, exposure and development processes for forming the etch barrier are performed one time. Since one exposure mask is employed, the counter electrode 12 a, the gate bus line 13 a and the common electrode line 14 a are deemed to be formed according to one photolithography process. In accordance with the present invention, a manufacturing time is reduced by performing one photolithography process, and a manufacturing cost is cut down by using one exposure mask, which results in improved productivity.
    [0031] Referring to FIG. 2B, a gate insulating film [0031] 15 is deposited on the glass substrate 1 where the counter electrode 12 a, the gate bus line 13 a and the common electrode line 14 a have been formed. An undoped amorphous silicon film and a doped amorphous silicon film are sequentially deposited on the gate insulating film 15. Thereafter, the doped amorphous silicon film and the undoped amorphous silicon film are patterned according to a second photolithography process, thereby forming an ohmic contact layer 17 and a channel layer 16. A metal film for source/drain is deposited over the resultant structure. The metal film for the source/drain is patterned according to a third photolithography process, thereby forming a data bus line(not shown) including source and drain electrodes 18 a, 18 b. Thus, a thin film transistor (TFT) is formed.
    [0032] Referring to FIG. 2C, a passivation film [0032] 19 such as a silicon nitride film is deposited over the resultant structure in order to protect the TFT. Thereafter, the passivation film 19 is etched according to a fourth photolithography process so that the source electrodes 18 a can be exposed. An ITO film as a transparent metal film is deposited on the passivation film 19. The ITO film is patterned according to a fifth photolithography process, thereby forming a comb-shaped pixel electrode 20 having a few branches and contacting with the source electrodes 18 a.
    [0033] As described above, in accordance with the present invention, the lower substrate in the FFS mode LCD is formed according to the five photolithography processes. As compared with the conventional method, the present invention omits one photolithography process, and thus increases productivity. [0033]
    [0034] Various other modifications to the basic process will be apparent to and can be readily made by those skilled in the art without departing from the scope and spirit of the present invention. [0034]
    权利要求:
    Claims (7)
    [1" id="US-20010007779-A1-CLM-00001] 1. A method for manufacturing a fringe field switching mode liquid crystal display device, comprising the steps of:
    forming a counter electrode, a gate bus line and a common electrode line at the same time, by sequentially depositing an indium tin oxide film and an MoW film on a glass substrate, and patterning the MoW film and the ITO film according to a first photolithography process;
    depositing a gate insulating film over the resultant structure;
    forming a stacked channel layer and ohmic contact layer on a predetermined portion of the gate insulating film, by using a second photolithography process;
    forming a data bus line including source/drain electrodes on the ohmic contact layer and the gate insulting film, by using a third photolithography process;
    forming a passivation film to expose the source electrode over the resultant structure, by using a fourth photolithography process; and
    forming a pixel electrode of a comb shape in contact with the source electrode on the passivation film, by using a fifth photolithography process,
    wherein the first photolithography process comprises:
    a first process for coating a resist film on the MoW film;
    a second process for forming a resist pattern consisting of first and second patterns respectively covering gate bus line and common electrode line formation regions and maintaining a coating thickness, and a third pattern covering a counter electrode formation region and partially maintaining the coating thickness, by exposing/developing the resist film;
    a third process for forming the gate bus line and the common electrode line by dry-etching the MoW film using the resist pattern as an etch barrier, the first and second patterns being partially removed, the third pattern being completely removed, the MoW film on the counter electrode formation region being partially removed;
    a fourth process for forming the counter electrode by wet-etching the ITO film using the remained resist pattern and MoW film as an etch barrier; and
    a fifth process for removing the remained resist pattern and MoW film.
    [2" id="US-20010007779-A1-CLM-00002] 2. The method according to
    claim 1 , wherein the exposure process for the resist film is performed by using a semipermeable mask where a chrome pattern for defining light permeable region and shield region is formed on a quartz substrate, and semipermeable patterns for decreasing a light permeable amount are formed in a predetermined permeable region.
    [3" id="US-20010007779-A1-CLM-00003] 3. The method according to
    claim 2 , wherein the semipermeable patterns are stripe type chrome patterns, or low permeable metal films consisting of an ITO film.
    [4" id="US-20010007779-A1-CLM-00004] 4. The method according to
    claim 1 , wherein the ITO film for the counter electrode is deposited at a thickness from 500 to 1,000 Å.
    [5" id="US-20010007779-A1-CLM-00005] 5. The method according to
    claim 1 , wherein the resist film is coated at a thickness from 2 to 3 μm.
    [6" id="US-20010007779-A1-CLM-00006] 6. The method according to
    claim 1 , wherein the dry etching process for the MoW film is performed by using a mixed gas of an excited gas, such as SF6, CF4 or He, and O2 gas.
    [7" id="US-20010007779-A1-CLM-00007] 7. The method according to
    claim 6 , wherein a flow rate ratio of the O2 gas and the excited gas satisfies following equation: O 2     gas     flow     rate excited     gas     flow     rate < 1 equation
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    2000-12-15| AS| Assignment|Owner name: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD., KOREA, R Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, KYUNG HA;CHO, SUNG HYUN;REEL/FRAME:011384/0610 Effective date: 20001211 |
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    优先权:
    申请号 | 申请日 | 专利标题
    KR99-60325||1999-12-22||
    KR1019990060325A|KR100325079B1|1999-12-22|1999-12-22|Method of manufacturing lcd having high aperture ratio and high transmittance|
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